Hi! I am Mark,

a postdoc working at the Fraunhofer Institute for Integrated Circuits IIS in Nürnberg where I am a researcher in the group “Effient-AI”.

My work centers on efficient design and compression of deep neural networks (DNNs) for deployment on embedded edge devices, particularly Cortex-M microcontrollers (MCUs) and Cortex-A system-on-chips (SoCs). Often called “Efficient AI,” this field addresses the mismatch between resource-limited hardware and the heavy demands of most DNNs. My main interest lies in balancing resource needs with achievable accuracy so these models can run on embedded systems. I emphasize hardware-aware neural architecture search (NAS), DNN compression, quantization methods, and MCU-specific finetuning. I am also exploring on-device training of fully quantized DNNs and continual learning within tight resource limits.

Efficient AI

Artificial intelligence and self-learning edge devices are gaining relevance for process automation and large-scale data analysis. Previously, a typical method linked “intelligent” edge systems to the cloud to handle AI inference, since most models, and particularly DNNs, demand computing power that the edge often lacks.

Efficient AI research aims to shift inference and training toward the edge by streamlining models. This approach offers several advantages: First, processing data near sensors on smaller, energy-efficient MCUs lowers power use, making execution both cheaper and more economical. Second, edge inference cuts round-trip time from acquisition to prediction by avoiding network communication that may be unreliable. Third, edge AI improves security because sensitive data is handled locally on the sensor node and never transmitted or stored externally.

To enable AI inference at the edge, efficient AI research focuses on efficient DNN design, training, and compression. This create a multi-objective optimization problem. AI performance, e.g., classification accuracy, should be maximized, while computational complexity and memory requirements should be minimized to meet the resource constraints of the targeted edge device. Techniques to achieve this trade-off include DNN pruning, quantization, layer fusion, and hardware-aware neural architecture search.

For more information, check out my talks and publications. If you would like to observe Edge AI in action, you can view my demo videos.

My background and history

I received both my M.Sc. and B.Sc. in computer science from the Friedrich-Alexander-Universität of Erlangen-Nürnberg. During my studies, I worked for almost five years as a working student at Siemens and then as a student assistant at Fraunhofer IIS, first in the group Self-Learning Systems and later in the group Machine Learning & Validation. I also wrote my master’s thesis with Fraunhofer IIS on Energy Efficient Deployment of Deep Learning Applications on Restricted Hardware using Deep Compression. After graduating, I joined the chair of Hardware-Software-Co-Design at FAU as a Ph.D. student, while remaining associated with Fraunhofer IIS as a member of the Efficient AI group. If you want to learn more about me, have a look at my detailed CV.